A Delta-Sigma modulator conventionally comprises an analogue loop filter, which may notably be low-pass, high-pass or bandpass, followed by an analogue-digital converter. The modulator also comprises at least one return digital-analogue converter. This converter comprises, in the case of a multi-bit modulator, several current or voltage sources, having mismatch errors, where these errors may vary depending on the environmental conditions: temperature, power supply voltage, or aging of the components.
The interest of a Delta-Sigma modulator resides in its high output resolution possible (up to 16, 24, 32 bits, or even more) for input signals with a moderate bandwidth. However, in a multi-bit Delta-Sigma modulator, the performance characteristics are limited by the mismatch errors of the return digital-analogue converter.
Various techniques are known for improving the linearity of the return digital-analogue converter.
The IEEE article by Bolatkale et al., entitled “A 4 GHz Continuous-Time ΔΣ ADC with 70 dB DR and −74 dBFS THD in 125 MHz BW”, provides a multi-bit return digital-analogue converter whose unit cells are dimensioned so as to minimize the mismatch error. Since the matching precision is reduced in proportion to the square root of the surface area of the unit cells, such an implementation leads to circuits with a large size, reduced speed and high power consumption.
Another known solution is to use mixing techniques, notably the DEM (Dynamic Element Matching) technique, in the multi-bit return digital-analogue converter. This technique consists in dynamically interchanging the selection of the unit cells of the converter in order to average the mismatch error noise. The DEM technique is not efficient at low over-sampling factors. Moreover, the digital circuit required for implementing the DEM technique adds latency on the path between the analogue-digital converter and the return digital-analogue converter, increasing the time constant of the loop and thus adversely affecting the speed of the clock and the bandwidth of the signal. Lastly, the DEM technique increases the number of switching operations of the unit cells which renders the digital-analogue converter of the return loop more vulnerable to transient errors.
Another solution for improving the linearity of the return digital-analogue converter is to calibrate its unit cells at start-up, as is the case in the IEEE article by Y. Dong et al., entitled “A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS”. This solution is not very robust because the environmental conditions, together with the characteristics of the unit cells, vary over time. This correction technique furthermore imposes that the modulator be in standby mode during the calibration.
In the IEEE articles by P. Witte et al., entitled “Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters” and J. G. Kauffman et al., entitled “An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR”, an online correction circuit for the unit cells of the multi-bit return digital-analogue converter is provided. A test unit cell is added and controlled by a pseudo-random binary sequence. The mismatch error is detected by a crossed correlation between the output of the modulator and the pseudo-random binary sequence. The precision of the correction is limited because the mismatch errors are not addressed at the source but in the digital domain. Furthermore, the pseudo-random signal is not perfectly subtracted in the digital domain and hence adds noise to the useful signal. The dynamic range of the modulator is also reduced due to the added pseudo-random signal, and the correction circuit consumes a significant amount of power degrading the energy efficiency of the modulator.
In the IEEE article by Kauffman et al. “A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW”, the authors add to the return digital-analogue converter an auxiliary digital-analogue converter which compensates the non-linearity of the main converter. However, since the compensation is applied for each mismatch error of the unit cells, this raises several difficulties:                the precision of the correction depends on the linearity of the auxiliary converter,        a fast LUT (Look Up Table) is required,        the auxiliary converter operates at a fraction of the dynamic range of the main converter and the mismatch error between the two is non-negligible.        
In the IEEE article by K. Falakshahi et al., entitled “A 14-bit, 10-Msamples/s D/A Converter Using Multibit ΣΔ Modulation”, the idea of the authors is to calibrate the unit cells of the return digital-analogue converter by storing a reference voltage in a capacitor. Owing to the leakage currents at the drain-substrate junctions, the calibration needs to be continually refreshed. In addition, the injection of charges due to the switching of the calibration selector switches degrades the precision of the voltage across the terminals of the capacitor. Furthermore, a three-channel selector switch is needed, the third channel being allocated to the calibration, complicating the implementation of the circuit and limiting its performance.
There exists a need to further improve Delta-Sigma modulators for correcting the mismatch errors, while at the same time maintaining good performance characteristics, notably in terms of precision, of speed and of energy consumption.